Use dmy dates date February 2012 Use Australian English date February 2012 Marguerite McKinnon born July, 1970 , ref name Scratch http home.sprintmail.com donburns scratchpad id2.html Interview Scratchpad . August 2007. Verify credibility date May 2009 ref is an Australia n journalist and television reporter for Seven News in Sydney , New South Wales , Australia . ref name Seven http seven.com.au news profile 050122 margueritemckinnon McKinnon s profile . the Seven News website. ref Born at the Mater Hospital in Sydney, McKinnon was the sixth child to Eric and Rosemary McKinnon, she has four brothers and three sisters. Eric McKinnon, a Korean War veteran, was also a teacher at several schools including St Paul s College Manly where he taught ceramics. Rosemary McKinnon, a former flight attendant for Qantas Airways prior to her marriage to Eric, has a degree in Rehabilitation Counseling from University of Sydney , where she was a member of the Golden Key International Honour Society . ref name Scratch McKinnon, is a Catholic , and along with her brothers and sisters, she attended St. Kieran s School in Manly Vale for primary education, and Stella Maris College Manly Stella Maris College Manly for secondary education. In Year 12 senior year McKinnon was named School Captain . McKinnon completed a BA Communications degree at Charles Sturt University . Mitchell campus, in Bathurst, New South Wales Bathurst , McKinnon began her career at Network Ten in Sydney, she then became a snow reporter at the ski resort Thredbo, New South Wales . She also worked at Radio 2XL Cooma, New South Wales, Radio FM 104.7 Canberra, WIN Television Orange NSW and Canberra and Radio 2UE Federal Parliament, before moving to Channel Seven Sydney where she worked as a news journalist for 5 years. She currently works for Channel Seven s current affairs program Today Tonight . McKinnon is also a columnist for small business publication, NETT Magazine . She is an ambassador for Life Changing Experie ... more details
more in the way of inter thread communication and scratchpad style workspace associated with the threads ... Layer Microsoft Robotics Studio Scratchpad RAM relevant to the distributed memory architecture of the Ageia ... more details
More footnotes date September 2011 Image Cyrix 6x86 P166.jpg right thumb 180px Cyrix 6x86 P166. The Cyrix 6x86 codename M1 is a sixth generation, 32 bit 80x86 compatible microprocessor designed by Cyrix and manufactured by International Business Machines IBM and SGS Thomson . It was originally released in 1996. Architecture Image Cyrix 6x86 arch.svg 250px thumb A simplistic block diagram of the Cyrix 6x86 microarchitecture . The 6x86 is superscalar and superpipelined and performs register renaming , speculative execution , out of order execution , and data dependency removal. However, it continued to use native x86 execution and ordinary microcode only, like Centaur Technology Centaur s Winchip , unlike competitors Intel and AMD which introduced the method of dynamic translation to micro operation s with Pentium Pro and AMD K5 K5 . With regard to internal caches, it has a 16 Kilobyte kB primary CPU cache cache and is CPU socket socket compatible with the Intel P5 microarchitecture P54C P54C Pentium brand Pentium . It was also unique in that it was the only x86 design to incorporate a 256 byte Level 0 scratchpad cache. It has six performance levels PR 90 , PR 120 , PR 133 , PR 150 , PR 166 and PR 200 . These performance levels do not map to the clock speed of the chip itself for example, a PR 133 ran at 110 MHz, a PR 166 ran at 133 MHz, etc. . The 6x86 and 6x86L weren t completely compatible with the Intel P5 microarchitecture P5 Pentium brand Pentium instruction set and is not multi processor capable. For this reason, the chip identified itself as a Intel 80486 80486 and disabled the CPUID instruction by default. CPUID support could be enabled by first enabling extended CCR registers then setting bit 7 in CCR4. The lack of full P5 Pentium compatibility caused problems with some applications because programmers had begun to use P5 Pentium specific instructions. Some companies released patches for their products to make them function on the 6x86. The first g ... more details
primary sources date February 2012 refimprove date February 2012 The Adolescence of P 1 is a 1977 science fiction novel by Thomas J. Ryan author Thomas J. Ryan , published by Macmillan Publishing, and in 1984 adapted into a Canadian made TV film entitled Hide and Seek . It features a Hacker computer security hacker who creates an artificial intelligence named P 1, which goes rogue and takes over computers in its desire to survive and seek out its creator. The book questions the value of human life, and what it means to be human. It is one of the first fictional depictions of the nature of a computer virus and how it can spread through a computer system, although predated by John Brunner novelist John Brunner s The Shockwave Rider . Plot The story starts in 1974 with the protagonist, Gregory Burgess, enrolled at Waterloo University in Canada. At the time Greg is aimless, taking various liberal arts courses and doing just well enough not to get kicked out of school. Everything changes one day when his friends introduce him to the IBM System 360 Mainframe computer mainframe and he becomes hooked , changing his major to computer science . During this time he also meets his on again off again girlfriend, Linda, a minor recurring character. After reading a Scientific American article on game theory outlining how to teach matchboxes to play tic tac toe , he becomes interested in using artificial intelligence techniques to crack systems. After manually cracking the university s 360 he sets aside a portion of memory to experiment in, calling it P 1 , suitably cryptic so operators would not notice it. He then uses this area of memory as an experimental scratchpad to develop a program known as The System. The System follows any telecommunications links it can find to other computers, attempting to compromise them in the same way, and remembering failed attempts to tune future attacks. If successful, The System sets up another P 1 on that computer, and injects itself and everyt ... more details
had only 256 bytes of scratchpad memory to support the storage of workspaces. This memory was placed ... of scratchpad RAM was available on the 16 bit bus. All other memory and peripherals were connected ... Instruments Compact Computer 40 . CPU RAM and Scratchpad The TI minicomputer inspired architecture ... the same internal one byte tokens as does TI s Extended BASIC, and many of the memory scratchpad ... upgrade option but was a user designed modification , 256 bytes CPU fast scratchpad RAM intended ... more details
. Array text 1 Limit of character Scratchpad for the output. Constant tdigit 0 9 of character 0 , 1 ... decision is in the choice of the base of arithmetic, here ten. There are many considerations. The scratchpad ... more details
In computer science , channel I O is a generic term that refers to a high performance input output I O architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computer s. In the past they were generally implemented with a custom processor, known alternately as peripheral processor , I O processor , I O controller , or DMA controller . Basic principles Many I O tasks can be complex and require logic to be applied to the data to convert formats and other similar duties. In these situations, the simplest solution is to ask the CPU to handle the logic, but because I O devices are relatively slow, a CPU could waste time in computer perspective waiting for the data from the device. This situation is called I O bound . Channel architecture avoids this problem by using a separate, independent, low cost processor. Channel processors are simple, but self contained, with minimal logic and sufficient on board scratchpad memory working storage to handle I O tasks. They are typically not powerful or flexible enough to be used as a computer on their own and can be construed as a form of coprocessor . A CPU sends relatively small channel program s to the controller via the channel to handle I O tasks, which the channel and controller can, in many cases, complete without further intervention from the CPU exception those channel programs which utilize program controlled interrupts , PCIs, to facilitate program loading, demand paging and other essential system tasks . When I O transfer is complete or an error is detected, the controller communicates with the CPU through the channel using an interrupt . Since the channel has direct access to the main memory, it is also often referred to as DMA controller where DMA stands for direct memory access , although that term is looser in definition and is often applied to non programmable devices as well. History The first use of channel I O was with the IBM 709 ref http www 03.ibm.com ib ... more details
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