For Verilog HDL Verilog unreferenced date November 2010 infobox programming language name VHDL logo paradigm ... view.cgi P1076 WebHome IEEE VASG File Vhdl signed adder.png thumb VHDL source for a signed Adder electronics adder . VHDL VHSIC hardware description language is a hardware description language used in electronic ... VHDL was originally developed at the behest of the United States Department of Defense U.S Department ... that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative ... were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit ... of Ada, citation needed date November 2010 VHDL borrows heavily from the Ada programming language Ada programming language in both concepts and syntax . The initial version of VHDL, designed to IEEE ... known as VHDL AMS provided analog and mixed signal circuit design extensions. Some other standards support wider use of VHDL, notably VITAL VHDL Initiative Towards ASIC Libraries and microwave circuit design extensions. In June 2006, the VHDL Technical Committee of Accellera delegated by IEEE to work on the next update of the standard approved so called Draft 3.0 of VHDL 2006. While maintaining ... writing and managing VHDL code easier. Key changes include incorporation of child standards 1164 ... Property Specification Language . These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system level descriptions. In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 ..., Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076 2008. The VHDL standard IEEE 1076 2008 was published in January 2009. Design VHDL is commonly used to write text models ... is commonly called a testbench . VHDL has constructs to handle the parallel computing parallelism ... more details
VHDL AMS is a derivative of the hardware description language VHDL IEEE standard 1076 1993 . It includes analog and mixed signal extensions AMS in order to define the behavior of analog and mixed signal systems IEEE 1076.1 1999 . The VHDL AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high level behavioral descriptions as well as structural descriptions of systems and components. ref Christen E., Bakalar K., VHDL AMS a hardware description language for analog and mixed signal applications ,Circuits and Systems II Analog and Digital Signal Processing, IEEE Transactions on see also Circuits and Systems II Express Briefs, IEEE Transactions on Volume 46, Issue 10, Oct. 1999, pp. 1263 1272. ref VHDL AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous time and event driven modeling semantics, and so is suitable for analog, digital, and mixed analog digital circuits. It is particularly well suited for verification of very complex analog, mixed signal and radio frequency integrated circuits. Code example In VHDL AMS, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations . A simple ideal diode in VHDL AMS would look something like this source lang VHDL this is a VHDL comment import electrical system from the disciplines library library IEEE, disciplines use IEEE.math real.all use disciplines.electrical system.all this is the entity entity DIODE is generic iss REAL 1.0e 14 Saturation current af REAL 1.0 Flicker noise coefficient ... VHSIC hardware description language VHDL IEEE 1076 Electronic design automation Very large scale ... saber Synopsys Saber Category Hardware description languages de VHDL AMS fr VHDL AMS he VHDL ... more details
The IEEE Standard 1076 defines the VHSIC Hardware Description Language or VHDL . It was originally developed under contract F33615 83 C 1003 from the United States Air Force awarded in 1983 to a team with Intermetrics, Inc. as language experts and prime contractor, with Texas Instruments as chip design experts and IBM as computer system design experts. The language has undergone numerous revisions and has a variety of sub standards associated with it that augment or extend it in important ways. citation needed date August 2011 1076 was and continues to be a milestone in the design of electronic systems. citation needed date August 2011 Revisions 1076 1987 First standardized revision of ver 7.2 of the language from the United States Air Force. 1076 1993 ISBN 1 55937 376 8 Significant improvements resulting from several years of feedback. Probably the most widely used version with the greatest vendor tool support. 1076 2000 Minor revision. Introduces the use of protected types . 1076 2002 Minor revision of 1076 2000. Rules with regard to buffer ports are relaxed. 1076 2008 previously referred to as 1076 200x Major revision released on 2009 01 26. Among other changes, this standard introduces the use of external signals . Related standards IEEE 1076.1 VHDL Analog and Mixed Signal IEEE 1076.1.1 VHDL AMS Standard Packages stdpkgs IEEE 1076.2 VHDL Math Package math IEEE 1076.3 VHDL Synthesis Package vhdlsynth IEEE 1076.3 VHDL Synthesis Package Floating Point fphdl IEEE 1076.4 Timing VHDL Initiative Towards ASIC Libraries vital IEEE 1076.6 VHDL Synthesis Interoperability IEEE 1164 VHDL Multivalue Logic std logic 1164 Packages IEEE standards Category IEEE standards Category IEEE DASC standards Category Hardware description languages standard stub fr IEEE 1076 ... more details
infobox software name Incisive developer Cadence Design Systems operating system Cross platform genre Simulator license proprietary website http www.cadence.com products fv Pages default.aspx Cadence Functional Verification Incisive is a suite of tools from Cadence Design Systems related to the design and verification of ASIC s, SoC s, and FPGA s. Incisive is commonly referred to by the name NCSim in reference to the core simulation engine. In the late 1990s, the tool suite was known as ldv logic design and verification . Depending on the design requirements, Incisive has many different bundling options of the following tools class wikitable Tool command description NC Verilog ncvlog Compiler for Verilog 95, Verilog 2001 and SystemVerilog NC VHDL ncvhdl Compiler for VHDL 87, VHDL 93 NC SystemC ncsc Compiler for SystemC NC Elaborator ncelab Unified linker elaborator for Verilog, VHDL, and SystemC libraries. Generates a simulation object file referred to as a snapshot image . NC Sim ncsim Unified simulation engine for Verilog, VHDL, and SystemC. Loads snapshot images generated by NC Elaborator. This tool can be run in GUI mode or batch command line mode. In GUI mode, ncsim is similar to the debug features of ModelSim s vsim. Sim Vision simvision A standalone graphical waveform viewer and netlist tracer. This is very similar to Novas Software s Debussy. See also List of Verilog simulators Category Electronic design automation software Category Logic design ... more details
Orphan date January 2011 BHDL is method of correct design of digital circuit. It combines the advantages of VHDL , the well known language of circuit design, with the power of B method that guarantees the correct design w.r.t. a formal specification . This allows avoiding the design test since it is correct by proven construction . Relation between VHDL and B method The relation between the abstract machine and the refinement in B method in a B project seems like the Entity Architecture relation in a VHDL project. In BHDL, from an enriched VHDL notation, the main structure is captured and communicated to the main formal model in order to prove the consistency of the structure and the coherence in relation to the abstract architecture and with the other components of the system. From the graphical tool, VGUI, the main structure of the system is created. Then, two different notations are generated VHDL and B. The produced B method code contains the main features of VHDL one. After that, design may be separated in relation to the techno logic choices. For more flexibility, designer may write directly the enriched VHDL notation. References Ammar Aljer, Philippe Devienne, Sophie Tison Laboratoire d Informatique Fondamentale de Lille LIFL ,Jean Louis Boulanger HDS ,Georges Mariano Institut national de recherche sur les transports et leur s curit INRETS . http www.computer.org plugins dl pdf proceedings acsd 2003 1887 00 18870241.pdf?template 1&loginState 1&userData anonymous IP 253A 253AAddress 253A 2B69.22.172.150 252C 2B 255B172.16.161.5 252C 2B69.22.172.150 252C 2B127.0.0.1 255D BHDL Circuit design in B . 2003 IEEE A. Aljer & J. L. Boulanger Heudiasyc, Compiegne, France ,P. Devienne LIFL, Villeneuve d Ascq, France . B HDL circuit and safety properties Aljer A. 2004, Co Design and Refinement in B. PhD Thesis. USTL Lille. FOLDOC Category Formal methods Category Formal specification languages soft eng stub fr BHDL ... more details
orphan date January 2011 gedif command is the command line to work with edif file , the edif files can be created from xml description or vhdl file s, gedif command can make the schematic and behavioral description until the pcb description by automatic or manual routing function. edif ger file sch.edf edif pcb auto dxf file sch.edf file pcb.dxf edif pcb auto edf file sch.edf file pcb.edf but to create the vhdl file we can call the following command edif vhd file sch.edf External links Additional information can be found at https sourceforge.net projects gedif Category Linux ... more details
orphan date December 2007 The Design Automation Standards Committee DASC is a subgroup of interested individuals members of the Institute of Electrical and Electronics Engineers IEEE IEEE Standards Association Standards Association . It oversees IEEE Standards that are related to computer aided design known as design automation . It is part of the IEEE Computer Society . ref name site cite web title The Design Automation Standards Committee work official web site publisher IEEE url http www.dasc.org accessdate August 13, 2011 ref The biggest center of interest in the DASC has been around language based design and verification standards stemming from the key Hardware Description Language standards VHDL and Verilog . From these have flowed standards for timing, synthesis, math routines, test, power, encryption, and meta data for the topics above. The emphasis of the group has also grown to embrace standards being developed in analog mixed signal and other extensions driven by these needs. Standards sponsored by the DASC include IEEE 1076 Standard VHDL Language Reference Manual VASG http www.eda.org vasg VHDL 200x http www.eda.org vhdl 200x the next revision Issues Screening and Analysis Committee ISAC http www.eda.org isac VHDL Programming Language Interface Task Force VHPI http www.eda.org vhdlpli P1076.1 Standard VHDL Analog and Mixed Signal Extensions VHDL AMS P1076.1.1 Standard VHDL Analog and Mixed Signal Extensions Packages for Multiple Energy Domain Support StdPkgs P1076.4 Standard VITAL ASIC Application Specific Integrated Circuit Modeling Specification VITAL P1076.6 Standard for VHDL Register Transfer Level RTL Synthesis SIWG P1364.1 Standard for Verilog Register Transfer Level Synthesis VLOG Synth P1481 Standard for Integrated Circuit IC Open Library Architecture OLA IEEE1481R P1499 Standard Interface for Hardware Description Models of Electronic Components OMF P1603 Standard for an Advanced Library Format ALF Describing Integrated Circuit IC Technology, Cel ... more details
In digital logic , a don t care term is an input sequence a series of bits to a function that the designer does not care about, usually because that input would never happen, or because differences in that input would not result in any changes to the output. By considering these don t care inputs, designers can potentially minimize their function much more so than if the don t care inputs were taken to have an output of all 0 or all 1. Examples of don t care terms are the binary values 1010 through 1111 10 through 15 in decimal for a function that takes a Binary coded decimal BCD value, because a BCD value never takes on values from 1010 to 1111. Don t care terms are important to consider in minimizing, using Karnaugh map s and the Quine McCluskey algorithm . X value Don t care may also refer to an unknown value in a multi valued logic system, in which case it may also be called an X value . In the Verilog hardware description language such values are denoted by the letter X . In the VHDL hardware description language such values are denoted in the standard logic package by the letter X forced unknown or the letter W weak unknown . ref name VHDL cite book title Vhdl A Logic Synthesis Approach author David Naylor and Simon Jones year 1997 publisher Springer isbn 0412616505 pages 14&ndash 15,219,221 ref An X value does not exist in hardware. In simulation, an X value can result from two or more sources driving a signal simultaneously, or the stable output of a flip flop electronics not having been reached. In synthesized hardware, however, the actual value of such a signal will be either 0 or 1, but will not be determinable from the circuit s inputs. ref name VHDL See also Karnaugh map Quine McCluskey algorithm Decision table References references External sources DEFAULTSORT Don t Care Logic Category Logic compsci stub logic stub de Don t Care it Condizione di indifferenza th ... more details
In computer aided design, behavioral modeling is a high level Electronic circuit circuit modeling technique where behavior of logic is modeled. The Verilog AMS and VHDL AMS languages are widely used to model logic behavior. Other modeling approaches Register transfer level RTL Modeling logic is modeled at register level. Structural Modeling logic is modeled at both register level and gate level. References Analog Behavioral Modeling with the Verilog A Language by Dan FitzPatrick, Ira Miller. Category Computer aided design comp sci stub ... more details
Refimprove date August 2008 Notability date August 2008 Expand section year of introduction, information about how widespread its use is date August 2008 Warp is a VHDL low cost development system for CPLD by Cypress Semiconductor Corporation. The cost is low about 99 because of its simple architecture. Warp contains an interactive simulator Aldec and a compiler Galaxy . Unlike the IEEE 1164 standard, Warp supports only 6 logic levels 0 , 1 , Z , L , H and X strong drive logic unknown and W Weak drive unknown aren t supported. The arithmetic operators can be supported by system only if the appropriate library is linked. With Warp a project can be written only with VHDL both with behavioral and structural architecture. Aldec is the simulator that can do pre synthesis and post synthesis simulation. Pre synthesis simulation is useful to verify that VHDL program works as expected and post synthesis simulation keeps also propagation delay. Projecting steps VHDL or Verilog code writing with graphic editor Code simulation to verify that program works as expected Synthesis after choosing a specific device Automatic fitting mapping logic functions into PLD logic blocks Post synthesis simulation with timing informations At the end of the process ISR, a programming software, generates a jam file containing the bit streams needed to programming PLD macrocells. At the current date Dec. 2009 , Cypress Semiconductor have no longer Warp for sale because license agreement with Alder Simulator expired, however, Cypress still provides technical support for previous customers ref http www.cypress.com ?rID 35274 ref See also Cypress Semiconductor References Reflist External links http www.cypress.com ?rID 35274 Category Hardware description languages Electronics stub ... more details
VHD may refer to Video High Density VHD file format , or V irtual H ard D isk file format, a disk image format used by Microsoft Virtual PC Volumetric Haptic Display Vampire Hunter D Rabbit haemorrhagic disease , also known as Viral Haemorrhagic Disease VHDL , or V HSIC H ardware D escription L anguage Valvular heart disease Disambig de VHD fr VHD ... more details
Multiple issues unreferenced March 2009 context March 2009 orphan February 2009 wikify December 2010 In VHDL simulations, all signal assignments occur with some infinitesimal delay, known as delta delay . Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond fs . References Reflist DEFAULTSORT Delta Delay Category Hardware description languages simulation software stub ... more details
notability date October 2011 primary sources date October 2011 Esterel Studio is a design environment based on the Esterel language. It is optimized for hardware IP address IP s such as Direct memory access DMA s, protocols, cache controllers, I O subsystems, etc. dedicated at capturing formal design specifications, enabling formal verification of properties early in the design phase, and automating the production of synthesizable Register transfer language RTL VHDL and Verilog , both for prototyping and production purposes. Features Formal specification Formal executable specifications. Verification of properties and assertions. Synchronous programming language synchronous dataflow programming dataflow design. Generate specification in VHDL or Verilog formats. Generate C programming language C , C , or SystemC code. ECO Domain Driven Design ECO support. See also SyncCharts External links http www.synfora.com products esterelStudio.html Esterel Studio web page compu lang stub Category Synchronous programming languages Category Hardware description languages ... more details
B for i 0 i 8 i i 1 begin G i Bext i 1 Bext i end end endmodule source The generated VHDL code looks as follows source lang VHDL library IEEE use IEEE.std logic 1164.all use IEEE.numeric std.all use ... more details
Orphan date February 2009 Open Verification Library OVL is a library of property checkers for digital circuit descriptions written in popular hardware description language Hardware Description Languages HDLs . OVL is currently maintained by Accellera . Applications OVL works by placing modules or components checking specific properties of the circuit alongside regular modules or components. Those special modules are called checkers and are tied to circuit signals via ports . Some aspects of the checker functionality can be modified by adjusting checker parameters . Typical properties verified by OVL checkers include condition that should be always met, sequence of conditions that should be met, condition that should never occur, proper data value even, odd, within a range, etc. , proper value change e.g. increment or decrement within specified range , proper data encoding e.g. one hot or one cold , proper timing of event within given number of clock cycles or within window created by trigger events , valid protocol of data transmission, valid behavior of popular building blocks e.g. FIFO s . Depending on the selected parameters, OVL checkers can work as assertion, assumption or coverage point checkers. Main source of OVL popularity is the fact that it allows introducing high level verification concepts to the existing or new designs without requiring new language, e.g. a designer having access to Verilog tools does not need a new language to start using property checking with OVL. Supported Languages While first versions of OVL supported Verilog and VHDL , most recent versions support in alphabetical order Property Specification Language PSL Verilog flavour SystemVerilog Verilog VHDL Depending on the demand, support for two more languages may be added Property Specification Language PSL VHDL flavour and SystemC . External links OVL section of the Accellera page http www.accellera.org activities ovl OVL Users Site http www.eda stds.org ovl Category Hardware descripti ... more details
of C to HDL techniques. C to VHDL compilers are very useful for large designs or for implementing ... Cebatech PICO Express from http www.synfora.com Synfora SPARK a C to VHDL from http mesl.ucsd.edu spark ... index.php?option com content&task blogcategory&id 21&Itemid 43 Ylichron HercuLeS C assembly to VHDL tool with http www.nkavvadias.com cgi bin herc.cgi free web interface VLSI VHDL CAD Group Index of Useful ... chain MyHDL is a Python subset compiler and simulator to VHDL and or Verilog ref http www.myhdl.org ref GHDL is a VHDL simulator and compiler capable of calling functions or procedures written in a foreign ... initiative, some products listed and C to VHDL tools. http www.altium.com Evaluate DEMOcenter ,11,0,1,3 ... more details
A Bus Functional Model or BFM also known as a Transaction Verification Models or TVM is a non logic synthesis synthesizable software model of an integrated circuit component having one or more external buses. The emphasis of the model is on simulating system bus transactions prior to building and testing the actual hardware. BFM s are usually defined as tasks in Hardware description language s HDLs , which applies stimulus to the design under test verification via complex waveforms and protocols. A BFM is typically written in an HDL language such as verilog , VHDL , SystemC , or SystemVerilog . On one side, it drives and samples low level signals according to the bus protocol. On the other side, tasks are available to create and respond to bus transactions. BFMs are often used as reusable building blocks to create simulation test benches, where the signal ports on a design under test are connected to the appropriate BFMs in the software test bench test bench for the purpose of simulation. Transaction Verification Models BFMs are sometimes referred to as TVMs or Transaction Verification Models. This is to emphasize that bus operations of the model have been bundled into atomic bus transactions to make it easier to issue and view bus transactions. Viewing of bus transactions of TVMs is similar to viewing the output of a protocol analyzer or bus sniffer . External references http www.omimo.be Magazine 01q2 2001q2 p027.pdf Manual and Automatic VHDL Verilog Test Bench Coding Techniques Category Logic design Electron stub ... more details
The IEEE 1164 standard defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description. It was sponsored by the IEEE Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers IEEE . The standardization effort was based on the donation of the Synopsys MVL 9 type declaration. The primary data type std ulogic standard unresolved logic consists of nine character literals in the following order ref cite web title VHDL and Logic Synthesis url http iroi.seu.edu.cn books asics Book2 CH12 CH12.6.htm work publisher date accessdate 22 January 2010 ref class wikitable Character Value U uninitialized X strong drive, unknown logic value 0 strong drive, logic zero 1 strong drive, logic one Z high impedance W weak drive, unknown logic value L weak drive, logic zero H weak drive, logic one nowiki nowiki don t care This system promoted a useful set of logic values that typical CMOS logic design could utilize in the vast majority of modeling situations. The Z literal makes tri state buffer logic easy. The H and L weak drives permit wired AND and wired OR logic. Additionally, the U state is the default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary. In VHDL , the hardware designer makes the declarations visible via the following code library code and code use code statements source lang VHDL library IEEE use IEEE.std logic 1164.all source See also Four valued logic IEEE 1364 defines a four valued logic among other things References reflist colwidth 30em cite book author1 D. Michael Miller author2 Mitchell A. Thornton title Multiple valued logic concepts and representations year 2008 publisher Morgan & Claypool Publishers isbn 9781598291902 series S lc YNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS volume 12 IEEE standards Category IEEE standards Category IEEE DASC standards ... more details
In electronics, an adder electronics adder is a combinatorial or sequential logic element which computes the n 1 bit sum of two n bit numbers. The Brent Kung adder is one of the more advanced designs, having a gate level depth of math O log 2 n math . The Brent Kung adder is a parallel prefix form carry look ahead adder . It takes less area to implement than the Kogge Stone adder and has less wiring congestion, but lower performance. References citations date October 2011 reflist External links http www.acsel lab.com Projects fast adder adder designs.htm Adder Designs http www.openhdl.com vhdl 653 vhdl component brent kung adder generic.html Generic VHDL Implementation of the Brent Kung Adder Category Adders Compu hardware stub ... more details
Citations missing date July 2010 DIME C is a C to HDL tool developed by Nallatech it is part of their DIMEtalk Design Tools suite. It includes an editor, a compiler and a parallelization visualizer. It supports the majority of ANSI C. It generates VHDL. External links http www.nallatech.com Nallatech http www.nallatech.com index.php FPGA Development Tools dimetalk.html DIMEtalk page on Nallatech s website. http www.cse.clrc.ac.uk disco publications FPGA overview 2.0.pdf Daresbury Labs Overview an overview of flows by Daresbury Labs, includes DIME C. Category Gate arrays Category Electronic design automation software programming software stub ... more details
Multiple issues orphan December 2010 refimprove December 2010 notability December 2010 Gezel is a hardware description language , allowing the implementation of a Finite State Machine Datapath FSMD model. The tools included in Gezel allows for simulation, cosimulation as well as compiling into VHDL code. It is possible to extend Gezel through library blocks written in C ref name website http rijndael.ece.vt.edu gezel2 Main website for Gezel ref . A Hello World Program source lang Cpp dp helloWorld always display Hello World system S helloWorld source Notes references Category Hardware description languages Technology stub ... more details
to VHDL Full VHDL code used to achieve MSX2 compatibility default configuration A CD ROM with VHDL code examples and the following software Altera Quartus 2 Web Edition VHDL development environment ... more details
VHDL and Verilog simulation, and most importantly, are validated for timing accurate SDF annotated ... active hdl Active HDL Riviera http www.aldec.com Aldec VHDL 2002, V2001, SV2005 A simulator with complete ... Incisive Enterprise Simulator big 3 Cadence Design Systems VHDL 2002, V2001, SV2005 Cadence ... of the NCsim family, called Incisive Enterprise Simulator, includes Verilog, VHDL, and SystemVerilog ... http www.xilinx.com Xilinx VHDL 93, V2001 Xilinx s simulator comes bundled with the ISE Design ... Graphics VHDL 1076 1987, 1076 1993, 1076 2002, 1076 2008 , V2001, SV2005 The original Modeltech VHDL simulator was the first mixed language simulator capable of simulating VHDL and Verilog design entities ... Altera VHDL 1993, V2001, SV2005 Altera s simulator bundled with the Quartus II design software. Supports Verilog, VHDL and Altera Hardware Description Language AHDL . http www.simucad.com products ... smash smash overview.php SMASH http www.dolphin integration.com Dolphin Integration V1995, V2001, VHDL ... for analog descriptions, Verilog HDL and VHDL for digital, Verilog A AMS, VHDL AMS and ABCD a combination ... products simulation simulation.html VCS big 3 http www.synopsys.com Synopsys VHDL 2002, V2001 ... Functional superset C extensions inspired by Verilog, VHDL, Communicating Sequential Processes ... VHDL 1987 IEEE 1076 1987 VHDLVHDL 1993 IEEE 1076 1993 VHDLVHDL 2002 IEEE 1076 2002 VHDLVHDL 2008 IEEE 1076 2008 VHDL See also Verilog Waveform viewer DEFAULTSORT List Of Verilog Simulators Category ... more details
VHSIC was a 1980s United States of America U.S. government program to develop very high speed integrated circuits . The United States Department of Defense launched the VHSIC project in 1980 as a joint tri service Army Navy Air Force project. The project led to advances in integrated circuit materials, lithography, packaging, testing, and algorithms, and created numerous computer aided design tools. A well known part of the project s contribution is VHDL , a hardware description language. The program also redirected the military s interest in GaAs ICs back toward the commercial mainstream of CMOS circuits. ref Cite book title Advanced Signal Processing author David J. Creasey publisher IEE Telecommunications Series year 1985 isbn 0 86341 037 5 url http books.google.com books?id iszN4Ohe1b0C&pg PA134&ots 2VxlTp9rpn&dq VHSIC&as brr 3&sig Uw6t cKlpC0ZyuJ2y9uYufGCa4Y ref ref Cite book title Government Policy Towards Industry in the United States and Japan author John B. Shoven publisher Cambridge University Press year 1988 isbn 0 521 33325 3 url http books.google.com books?id hBpWgC4hcAcC&pg PA346&ots 7aHdkVzbwg&dq VHSIC&as brr 3&sig WEMtkwa 2NawUyLSjscWnvZiOis ref See also VHDL References Reflist Category Electronics Electronics stub es Very High Speed Integrated Circuit fr Very High Speed Integrated Circuit ko pt VHSIC ru VHSIC zh ... more details
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