In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel architectures, in which data values are sent all bits at once along a group of wires.

Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.^[1]

References

External links

• Application of [[FPGA] technology to accelerate the finite-difference time-domain (FDTD) method]
• BIT-Serial [[FIR filter]s with CSD Coefficients for FPGAs]